In the manufacturing process that forms fine patterns on a substrate such as a semiconductor and a liquid crystal, there is a change in a defect to be an analysis target along with the miniaturization of manufacturing patterns. Conventionally, a defect species, which is called as a random defect occurring from dusts and foreign particles, was a target to be analyzed in many cases. However, along with the introduction of an OPC (Optical Proximity Correction) technique, such a case that a systematic defect highly dependent on a layout of a design pattern should be a target to be analyzed has been increasing.
The systematic defect is the defect which occurs caused by specific patterns and layers or a combination of such patterns and layers, the systematic defect can be solved by changing design patterns and layouts, or by changing manufacturing conditions. Therefore, there has been an important problem in improvement of a yield ratio of the semiconductor manufacturing process that the patterns and layers or combinations of such patterns and layers having caused the systematic defect are efficiently specified.
As a technique for efficiently specifying the systematic defect, Patent Document 1 discloses a method in which defect coordinates and design layout data are overlaid (hereinafter, it will be referred to as “matching”) to specify patterns and layers in which a defect occurs. Further, Patent Document 2 discloses a technique in which a device pattern is extracted from an image where a semiconductor device is captured, and the extracted pattern and design layout data are overlaid to perform pattern measurements.